9dbl411b idt ? four output low power differential buffer for pci express gen1, gen2, and qpi 1645c?10/18/10 four output low power differential fanout buffer for pci express gen1, gen2, and qpi 1 datasheet recommended application: features/benefits: pci-express gen2 or qpi fanout buffer ? low power differential outputs for pci- express and qpi clocks ? power down mode when all oe# are high ? available in i-temp ? 20-pin mlf or tssop packaging output features: ? 4 - low power differential output pairs ? individual oe# control of each output pair general description: the 9dbl411b is a 4 output lower power differential buffer. each output has its own oe# pin. it has a maximum operating frequency of 150 mhz. functional block diagram power groups key specifications: ? output cycle-cycle jitter < 15ps additive ? output to output skew: < 50ps stop logic dif_int dif_inc dif_lpr(3:0) 4 oe#(3:0) 4 vdd gnd 9,18 10,17 vdd_io for dif(3:0) 4 5 3.3v analog vdd & gnd vdd gnd 6,15 7,14 vdd_io for dif(3:0) 1 2 3.3v analog vdd & gnd description pin number (tssop) pin number (mlf) description
idt ? four output low power differential buffer for pci express for gen1, gen2, and qpi 1645c?10/18/10 advance information 9dbl411b four output low power differential buffer for pci express gen1, gen2, and qpi 2 pin configurations rs rs zo zo 9dbl411 zo ? 17 = rs (ohms), where zo is the single-ended intrinsic impedance of the board transmission line. single-ended intrinsic impedance is ? that of the differential impedance. single ended impedance (zo) rs 5% tolerance rs 2% tolerance notes 50 33 33.2 45 27 27.4 42.5 24 or 27 24.9 in general, 5% resistors may be used. all values are in ohms. 20-pin mlf dif_int dif_inc oe0# dif0t_lpr dif0c_lpr 20 19 18 17 16 vdda 1 15 vdd_io gnda 2 14 gnd oe3# 3 13 oe1# dif3c_lpr 4 12 dif1t_lpr dif3t_lpr 5 11 dif1c_lpr 678910 vdd_io gnd dif2c_lpr dif2t_lpr oe2# 9dbl411b oe0# 1 20 dif0t_lpr dif_inc 2 19 dif0c_lpr dif_int 3 18 vdd_io vdda 4 17 gnd gnda 5 16 oe1# oe3# 6 15 dif1t_lpr dif3c_lpr 7 14 dif1c_lpr dif3t_lpr 8 13 oe2# vdd_io 9 12 dif2t_lpr gnd 10 11 dif2c_lpr 9dbl411b 20-pin tssop terminations
idt ? four output low power differential buffer for pci express for gen1, gen2, and qpi 1645c?10/18/10 advance information 9dbl411b four output low power differential buffer for pci express gen1, gen2, and qpi 3 tssop pin description pin # (tssop) pin name pin type description 1oe0# in output enable for dif0 output. control is as follows: 0 = enabled, 1 = low-low 2 dif_inc in complement side of differential input clock 3 dif_int in true side of differential input clock 4 vdda pwr 3.3v power for the analog core 5 gnda gnd ground for the analog core 6oe3# in output enable for dif3 output. control is as follows: 0 = enabled, 1 = low-low 7 dif3c_lpr out complement clock of low power differential clock pair. (no 50ohm shunt resistor to gnd needed) 8 dif3t_lpr out true clock of low power differential clock pair. (no 50ohm shunt resistor to gnd needed) 9 vdd_io pwr power supply for low power differential outputs, nominal 1.05v to 3.3v 10 gnd gnd ground pin 11 dif2c_lpr out complement clock of low power differential clock pair. (no 50ohm shunt resistor to gnd needed) 12 dif2t_lpr out true clock of low power differential clock pair. (no 50ohm shunt resistor to gnd needed) 13 oe2# in output enable for dif2 output. control is as follows: 0 = enabled, 1 = low-low 14 dif1c_lpr out complement clock of low power differential clock pair. (no 50ohm shunt resistor to gnd needed) 15 dif1t_lpr out true clock of low power differential clock pair. (no 50ohm shunt resistor to gnd needed) 16 oe1# in output enable for dif1 output. control is as follows: 0 = enabled, 1 = low-low 17 gnd gnd ground pin 18 vdd_io pwr power supply for low power differential outputs, nominal 1.05v to 3.3v 19 dif0c_lpr out complement clock of low power differential clock pair. (no 50ohm shunt resistor to gnd needed) 20 dif0t_lpr out true clock of low power differential clock pair. (no 50ohm shunt resistor to gnd needed)
idt ? four output low power differential buffer for pci express for gen1, gen2, and qpi 1645c?10/18/10 advance information 9dbl411b four output low power differential buffer for pci express gen1, gen2, and qpi 4 mlf pin description pin # (mlf) pin name pin type description 1 vdda pwr 3.3v power for the analog core 2 gnda gnd ground for the analog core 3oe3# in output enable for dif3 output. control is as follows: 0 = enabled, 1 = low-low 4 dif3c_lpr out complement clock of low power differential clock pair. (no 50ohm shunt resistor to gnd needed) 5 dif3t_lpr out true clock of low power differential clock pair. (no 50ohm shunt resistor to gnd needed) 6 vdd_io pwr power supply for low power differential outputs, nominal 1.05v to 3.3v 7 gnd gnd ground pin 8 dif2c_lpr out complement clock of low power differential clock pair. (no 50ohm shunt resistor to gnd needed) 9 dif2t_lpr out true clock of low power differential clock pair. (no 50ohm shunt resistor to gnd needed) 10 oe2# in output enable for dif2 output. control is as follows: 0 = enabled, 1 = low-low 11 dif1c_lpr out complement clock of low power differential clock pair. (no 50ohm shunt resistor to gnd needed) 12 dif1t_lpr out true clock of low power differential clock pair. (no 50ohm shunt resistor to gnd needed) 13 oe1# in output enable for dif1 output. control is as follows: 0 = enabled, 1 = low-low 14 gnd gnd ground pin 15 vdd_io pwr power supply for low power differential outputs, nominal 1.05v to 3.3v 16 dif0c_lpr out complement clock of low power differential clock pair. (no 50ohm shunt resistor to gnd needed) 17 dif0t_lpr out true clock of low power differential clock pair. (no 50ohm shunt resistor to gnd needed) 18 oe0# in output enable for dif0 output. control is as follows: 0 = enabled, 1 = low-low 19 dif_inc in complement side of differential input clock 20 dif_int in true side of differential input clock
idt ? four output low power differential buffer for pci express for gen1, gen2, and qpi 1645c?10/18/10 advance information 9dbl411b four output low power differential buffer for pci express gen1, gen2, and qpi 5 absolute maximum ratings parameter symbol conditions min max units notes maximum supply voltage vdda core supply voltage 4.6 v 1,7 maximum supply voltage vdd_io low-voltage differential i/o supply 0.99 3.8 v 1,7 maximum input voltage v ih 3.3v lvcmos inputs 4.6 v 1,7,8 minimum input voltage v il any input vss - 0.5 v 1,7 tambcom commercial range 0 70 c 1 tambind industrial range -40 85 c 1 storage temperature ts - -65 150 c1,7 input esd protection esd prot human body model 2000 v 1,7 ambient operating temp electrical characteristics - input/supply/common output parameters parameter symbol conditions min max units notes supply voltage vddxxx supply voltage 3.000 3.600 v 1 supply voltage vddxxx_io low-voltage differential i/o supply 0.99 3.600 v 1 input high voltage v ihse single-ended inputs 2 v dd + 0.3 v 1 input low voltage v ilse single-ended inputs v ss - 0.3 0.8 v 1 differential input high voltage v ihdif differential inputs (single-ended measurement) 600 1.15 v 1 differential input low voltage v ildif differential inputs (single-ended measurement) v ss - 0.3 300 v 1 input slew rate - dif_in dv/dt measured differentially 0.4 8 v/ns 2 input leakage current i in v in = v dd , v in = gnd -5 5 ua 1 i dd_3.3v vdda supply current 20 ma 1 i dd_io_133m vdd_io supply @ fop = 133mhz 20 ma 1 i dd_sb_3.3v vdda supply current, input stopped, oe# pins all high 750 ua 1 i dd_sbio vdd_io supply, input stopped, oe# pins all high 150 ua 1 input frequency f i v dd = 3.3 v 15 150 mhz 2 pin inductance l p in 7nh 1 c in logic inputs 1.5 5 pf 1 c out output pin capacitance 6 pf 1 oe# latency (at least one oe# is low) t oe#lat number of clocks to enable or disable output from assertion/deassertion of oe# 13periods1 clock stabilization time (from all oe# high to first oe# low). t stab delay from assertion of first oe# to first clock out (assumes input clock running) 150 ns 1 tdrive_oe# t droe# output enable after oe# de-assertion 10 ns 1 tfall_oe# t fa ll 5ns 1 trise_oe# t rise 5ns 1 operating supply current power down current (all oe# pins high) fall/rise time of oe# inputs input capacitance
idt ? four output low power differential buffer for pci express for gen1, gen2, and qpi 1645c?10/18/10 advance information 9dbl411b four output low power differential buffer for pci express gen1, gen2, and qpi 6 ac electrical characteristics - dif low power differential outputs parameter symbol conditions min max units notes rising edge slew rate t slr differential measurement 1.5 4 v/ns 1,2 falling edge slew rate t flr differential measurement 1.5 4 v/ns 1,2 slew rate variation t slvar single-ended measurement 20 % 1 maximum output voltage v high includes overshoot 1150 mv 1 minimum output voltage v low includes undershoot -300 mv 1 differential voltage swing v swing differential measurement 1200 mv 1 crossing point voltage v xabs single-ended measurement 300 550 mv 1,3,4 crossing point variation v xabsvar single-ended measurement 140 mv 1,3,5 duty cycle distortion d cycdis0 differential measurement, fin<=133.33mhz 3%1,6 additive cycle to cycle jitter difj c2cadd differential measurement, additive 15 ps 1 dif[3:0] skew dif skew differential measurement 50 ps 1 propagation delay t pd input to output delay 2.5 3.5 ns 1 additive phase jitter - pcie gen1 t phase_addpcig1 1.5mhz < 22mhz 6 ps pk-pk 1,9 additive phase jitter - pcie gen2 high band t phase_addpcig2hi high band is 1.5mhz to nyquist (50mhz) 0.16 ps rms 1,9 additive phase jitter pcie gen2 low band t phase_addpcig2lo low band is 10khz to 1.5mhz 0.07 ps rms 1,9 additive phase jitter qpi133 (6.4gbs, 12 ui) t phase_addqpi6g4 11mhz to 33mhz 0.04 ps rms 1,9 notes on electrical characteristics (all measurements use 9lrs3187b as clock source and r s =33ohms/c l =2pf test load): 1 guaranteed by design and characterization, not 100% tested in production. 2 slew rate measured through vswing centered around differential zero 3 vxabs is defined as the voltage where clk = clk# 4 only applies to the differential rising edge (clk rising and clk# falling) 9 the 9dbl411b has no pll, so the part itself contributes very little jitter to the input clock. but this also means that the 9db l411 cannot 'de-jitter' a noisy input clock. values calculated per pci sig and per intel clock jitter tool version 1.5 8 maximum input voltage is not to exceed maximum vdd 6 this figure refers to the maximum distortion of the input wave form. 5 defined as the total variation of all crossing voltages of clk rising and clk# falling. matching applies to rising edge rate of clk and falling edge of clk#. it is measured using a +/-75mv window centered on the average cross point where clk meets clk#. 7 operation under these conditions is neither implied, nor guaranteed.
idt ? four output low power differential buffer for pci express for gen1, gen2, and qpi 1645c?10/18/10 advance information 9dbl411b four output low power differential buffer for pci express gen1, gen2, and qpi 7 min max min max a--1.20--.047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.19 0.30 .007 .012 c 0.09 0.20 .0035 .008 d e e1 4.30 4.50 .169 .177 e l 0.45 0.75 .018 .030 n a 0808 aaa -- 0.10 -- .004 variations min max min max 20 6.40 6.60 .252 .260 10-0035 see variations see variations 0.65 basic reference doc.: jedec publication 95, mo-153 n see variations see variations d mm. d (inch) 20-lead, 4.40 mm. body, 0.65 mm. pitch tssop 6.40 basic 0.252 basic 0.0256 basic common dimensions in millimeters in inches common dimensions (173 mil) (25.6 mil) symbol index area index area 12 1 n d e1 e sea ting plane sea ting plane a1 a a2 e -c- -c- b c l aaa c 20-pin tssop package drawing and dimensions
idt ? four output low power differential buffer for pci express for gen1, gen2, and qpi 1645c?10/18/10 advance information 9dbl411b four output low power differential buffer for pci express gen1, gen2, and qpi 8 top v iew index area d sawn singula tion anvil singula tion a 0. 08 c c a3 a1 seating plane e2 e2 2 l (n -1)x e (ref.) (ref.) & n n ev en n e d2 2 d2 (re f.) & odd 1 2 e 2 (t yp.) if n & n are even (n -1)x (ref.) b thermal base n or chamfer 4x 0.6 x 0.6 max optional e d n n d d d dimensions symbol min. max. a0.81.0 a1 0 0.05 n 20 a3 n d 5 b 0.18 0.3 n e 5 e d x e basic 4.00 x 4.00 d2 min. / max. 2.00 / 2.25 e2 min. / max. 2.00 / 2.25 l min. / max. 0.45 / 0.65 ics 20l tolerance symbo l 0.50 basic dimensions 0.20 reference thermally enhanced, very thin, fine pitch quad flat / no lead plastic package 20-pin mlf package drawing and dimensions ordering information part / order number shipping packaging package temperature 9dbl411bklf tubes 20-pin mlf 0 to +70c 9dbl411bklft tape and reel 20-pin mlf 0 to +70c 9dbl411bglf tubes 20-pin tssop 0 to +70c 9dbl411bglft tape and reel 20-pin tssop 0 to +70c 9DBL411BKILF tubes 20-pin mlf -40 to +85c 9DBL411BKILFt tape and reel 20-pin mlf -40 to +85c 9dbl411bgilf tubes 20-pin tssop -40 to +85c 9dbl411bgilft tape and reel 20-pin tssop -40 to +85c "lf" suffix to the part number are the pb-free configuration and are rohs compliant. "b" is the device revision designator (will not correlate to the datasheet revision).
idt ? four output low power differential buffer for pci express for gen1, gen2, and qpi 1645c?10/18/10 advance information 9dbl411b four output low power differential buffer for pci express gen1, gen2, and qpi 9 innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support 408-284-6578 pcclockhelp@idt.com corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan idt singapore pte. ltd. 1 kallang sector #07-01/06 kolamayer industrial park singapore 349276 phone: 65-6-744-3356 fax: 65-6-744-1764 europe idt europe limited 321 kingston road leatherhead, surrey kt22 7tu england phone: 44-1372-363339 fax: 44-1372-378851 ? 2010 integrated device technology , inc. all rights reserved. product specifications subject to change without notice. idt, ic s, and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other br ands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa this product is protected by united states patent no. 7, 342, 420 and other patents. revision history rev. issue date description page # 0.1 1/8/2010 initial release. compared with a rev the following have changed: 1. added i-temp version 2. updated electrical tables for i-temp 3. revised phase jitter specs and added qpi. a 1/8/2010 released to final. b 4/23/2010 changed input frequency from 33 min to 15 mhz min 5 c 10/18/2010 updated suppl y volta g e min/max ratin g s. 5
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